Circuits, including processors, may be packaged to include an array of electrical contacts or package pads arranged in the form of a contact field having an inner perimeter and an outer perimeter. In some circuit packages, one or more power contacts are located inside the inner perimeter of the contact field.
When such packages are mounted to a circuit board, vias may be used as part of the electrical path from one or more circuit board power planes to the power contacts. However, as the package contact field connection density increases, and the array package pitch decreases, the available power plane connection area may be reduced. This reduction can be caused by the presence of antipads (i.e., clearance holes) introduced into the circuit board to accommodate various connection paths through the board. The planar area available to place connection traces may also be reduced due to the concentration of connection pads in the contact field.
As a result, the amount of power available to the circuit may also be reduced, contributing to power supply droop during peak power consumption periods. Moreover, vias used as a part of the power path may have a reduced cross-sectional area, increasing resistance and further reducing the power available to the circuit.